Rao et al. Res. Trends Int. J. Technol. Innov., January - March 2026, 1 (1) : 81-88
1International Institute of Information Technology Bangalore, Bangalore, India; 2Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal, India
Article History
Accepted : 12 Mar 2026
Published : 28 Mar 2026
Publication Issue
Volume 1, Issue 1
January - March 2026
Page Number81–88
Biopotential acquisition front-ends require operational amplifiers with sub-microvolt input-referred noise while operating within tight power budgets for wearable devices. This paper presents a two-stage folded-cascode CMOS operational amplifier designed in 180nm technology, employing chopper stabilisation to suppress flicker noise below 1Hz. Post-layout simulations show an input-referred noise of 0.82 microvolts RMS over a 0.5Hz to 100Hz bandwidth, a gain of 86dB, and power consumption of 38 microwatts from a 1.8V supply, meeting requirements for ECG and EEG acquisition channels.
Keywords - CMOS operational amplifier, low-noise design, chopper stabilization, biomedical instrumentation, analog front-end
Wearable biopotential monitors demand amplifiers that resolve microvolt-level signals such as EEG in the presence of flicker noise and DC electrode offset, all while operating from coin-cell power budgets, motivating chopper-stabilised low-noise analog front-end design.
A two-stage folded-cascode operational transconductance amplifier was designed in a 180nm CMOS process with a chopper modulator placed at the input stage operating at 4kHz to shift flicker noise out of the signal band, followed by a demodulator and low-pass filter at the output. The design was validated through Cadence Spectre post-layout simulation across process, voltage and temperature corners.
Post-layout simulation showed an input-referred noise of 0.82 microvolts RMS over a 0.5 to 100Hz bandwidth, open-loop gain of 86dB, phase margin of 61 degrees, and total power consumption of 38 microwatts from a 1.8V supply, with a common-mode rejection ratio exceeding 78dB across process corners.
The chopper-stabilised design achieves noise and power performance suitable for battery-powered ECG and EEG acquisition channels. Future work includes silicon fabrication and bench characterisation against the simulated results.
[1] Enz C. C. and Temes G. C., Circuit techniques for reducing offset in op-amps, Proceedings of the IEEE, 1996. [2] Harrison R. R. and Charles C., A low-power low-noise CMOS amplifier for neural recording, IEEE JSSC, 2003. [3] Denison T. et al., A 2 microwatt 100nV/rtHz chopper-stabilized instrumentation amplifier, IEEE JSSC, 2007.
© 2026 The Author(s). Published by IJEIA Editorial Office. This is an open access article under the Creative Commons Attribution 4.0 International License (CC BY 4.0).
Siddharth Rao, Pooja Agarwal (2026). Design of a Low-Noise CMOS Operational Amplifier for Biomedical Signal Acquisition Systems. IJEIA, 1(1), 81-88.