Wadhwani et al. Res. Trends Int. J. Technol. Innov., July - September 2026, 1 (3) : 34-41
1International Institute of Information Technology Bangalore, Bangalore, India; 2Department of Electronics and Communication Engineering, Delhi Technological University, New Delhi, India
Article History
Accepted : 28 Jun 2026
Published : 10 Jul 2026
Publication Issue
Volume 1, Issue 3
July - September 2026
Page Number34–41
Resource-constrained IoT edge devices require cryptographic cores that balance throughput, power and silicon area, favouring hardware implementations over software AES routines. This paper presents an 8-bit datapath AES-128 core implemented on a low-cost Artix-7 FPGA, optimised through composite-field S-box substitution to reduce logic utilisation. The design occupies 312 slice LUTs, achieves an encryption throughput of 34 Mbps at 100MHz, and reduces area by 41 percent relative to a standard lookup-table-based S-box implementation, at a modest 18 percent throughput cost.
Keywords - AES encryption, FPGA, IoT security, hardware cryptography, composite field arithmetic
Software AES implementations on microcontroller-class IoT devices often cannot meet both the throughput and energy budgets required for encrypting sensor data streams, motivating compact hardware AES cores implemented on low-cost FPGAs for edge gateway applications.
An 8-bit datapath AES-128 encryption core was designed in Verilog targeting a Xilinx Artix-7 FPGA, with the substitution-box implemented using composite-field arithmetic in GF((2^4)^2) rather than a conventional 256-entry lookup table, trading combinational logic depth for reduced memory-block usage, and verified against NIST AES test vectors.
The composite-field implementation occupied 312 slice LUTs and no block RAM, a 41 percent area reduction compared to a lookup-table-based baseline occupying 528 LUTs plus one BRAM, while achieving an encryption throughput of 34 Mbps at a 100MHz clock, an 18 percent reduction from the 41 Mbps achieved by the lookup-table baseline.
Composite-field S-box construction offers a favourable area-throughput tradeoff for AES cores targeting the smallest FPGA fabrics common in IoT edge gateways. Future work will extend the design to support AES-256 and authenticated encryption modes.
[1] NIST FIPS 197, Advanced Encryption Standard, National Institute of Standards and Technology, 2001. [2] Rudra A. et al., Efficient Rijndael encryption implementation with composite field arithmetic, CHES, 2001.
© 2026 The Author(s). Published by IJEIA Editorial Office. This is an open access article under the Creative Commons Attribution 4.0 International License (CC BY 4.0).
Yash Wadhwani, Simran Kaur (2026). FPGA Implementation of a Lightweight AES Encryption Core for IoT Edge Devices. IJEIA, 1(3), 34-41.